Integration with VAIOS

NavHAL is designed to operate independently of any execution framework and does not require a real-time operating system for its functionality. As a result, its integration with VAIOS is minimal and well-defined, ensuring a clear separation between hardware access and execution control.

Unlike tightly coupled HAL-RTOS designs, NavHAL does not embed scheduling logic, synchronization mechanisms, or task management within its implementation. All peripheral operations exposed by NavHAL remain identical whether the system is running in bare-metal mode or under VAIOS.

Interaction Model

When VAIOS is used, NavHAL functions are invoked within tasks managed by the scheduler, in the same manner as they would be called in a bare-metal loop. This ensures that:

• No changes are required in NavHAL APIs when transitioning between execution models

• Peripheral access semantics remain consistent

• Timing behavior is preserved and controlled externally by the scheduler

Defined Integration Points

The interaction between NavHAL and VAIOS is limited to a small number of well-defined mechanisms:

• System Tick (SysTick): The SysTick interrupt is used by VAIOS as the primary timing source for scheduling. NavHAL provides the low-level configuration, while VAIOS utilizes it for task management.

• PendSV Interrupt: PendSV is used by VAIOS for context switching. NavHAL exposes interrupt control and handler linkage, allowing VAIOS to implement its scheduling mechanism without modifying HAL internals.

• Interrupt Callback Mechanism: NavHAL provides a generic interrupt attachment interface (hal_interrupt_attach_callback), which VAIOS uses to bind scheduler-related handlers and peripheral-driven events.

• Communication Interfaces (UART/USB): Peripheral drivers such as UART (and future USB CDC) are used by VAIOS for logging, telemetry, and debugging. NavHAL handles the hardware interaction, while VAIOS defines how and when data is processed.

Concurrency Model

NavHAL itself does not implement any concurrency control mechanisms such as mutexes, locks, or resource arbitration. This design choice ensures minimal overhead and deterministic behavior.

When VAIOS is present:

• Task scheduling and concurrency management are handled entirely by VAIOS

• Prevention of concurrent peripheral access is the responsibility of the execution layer

• NavHAL remains a stateless access layer with no knowledge of task context

Design Implication

This separation results in a clean architectural boundary:

NavHAL focuses solely on efficient and deterministic interaction with hardware, while VAIOS manages when and how these interactions occur.